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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR
ICS843031-01
GENERAL DESCRIPTION
The ICS843031-01 is an 10Gb Ethernet Clock ICS Generator and a member of the HiPerClocks TM HiPerClockSTM family of high performance devices from IDT. The ICS843031-01 uses an 18pF parallel resonant crystal. The ICS843031-01 has excellent <1ps phase jitter perfor mance, over the 1.875MHz - 20MHz integration range. The ICS843031-01 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
FEATURES
* One differential 3.3V or 2.5V LVPECL output * Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal * Output frequencies: 280MHz - 340MHz * VCO range: 560MHz - 680MHz * RMS phase jitter @ 312.5MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.46ps (typical) * Full 3.3V or 2.5V operating supply * 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
COMMON CONFIGURATION TABLE
Inputs Crystal Frequency (MHz) 25 M 25 N 2 Multiplication Value M/N 25 Output Frequency (MHz) 312.5
BLOCK DIAGRAM
OE Pullup
PIN ASSIGNMENT
VCCA VEE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VCC Q nQ OE
XTAL_IN
OSC
XTAL_OUT
Phase Detector
VCO
N = /2 (fixed)
Q nQ
ICS843031-01
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
M = /25 (fixed)
IDT TM / ICSTM 3.3V, 2.5V LVPECL CLOCK GENERATOR
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TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 4 5 6, 7 8 Name VCCA VEE XTAL_OUT, XTAL_IN OE nQ, Q VCC Power Power Input Input Output Power Pullup Type Description Analog supply pin. Negative supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Output Enable pin. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels. Power supply pin.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
TABLE 3. OE FUNCTION TABLE
Input OE 0 1 Outputs Q/nQ Hi-Z Enabled
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5V 50mA 100mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 101.7C/W (0 mps)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VCC V CCA I CCA I EE Parameter Power Supply Voltage Analog Supply Voltage Analog Supply Current Power Supply Current Test Conditions Minimum 3.135 VCC - 0.12 Typical 3.3 3.3 Maximum 3.465 3.465 12 105 Units V V mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V5%, TA = 0C TO 70C
Symbol VCC V CCA I CCA I EE Parameter Power Supply Voltage Analog Supply Voltage Analog Supply Current Power Supply Current Test Conditions Minimum 2.375 VCC - 0.12 Typical 2.5 2.5 Maximum 2.625 2.625 12 90 Units V V mA mA
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions VCC = 3.3V VCC = 2.5V VCC = 3.3V VCC = 2.5V VCC = VIN = 3.465V or 2.625V VCC = 3.465V or 2.625V, VIN = 0V -150 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VCC + 0.3 VCC + 0.3 0.8 0.7 5 Units V V V V A A
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TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum V CC - 1.4 V CC - 2.0 0.6 Typical Maximum V CC - 0.9 V CC - 1.7 1. 0 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 22.4 Test Conditions Minimum Typical Fundamental 25 27.2 40 7 300 MHz pF mW Maximum Units
TABLE 6A. AC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time Test Conditions 312.5MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% Minimum 280 Typical 312.5 0.46 150 48 500 52 Maximum 340 Units MHz ps ps %
tjit(O)
t R / tF
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section.
TABLE 6B. AC CHARACTERISTICS, VCC = 2.5V5%, TA = 0C TO 70C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time Test Conditions 312.5MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% Minimum 280 Typical 312.5 0.48 150 48 500 52 Maximum 340 Units MHz ps ps %
tjit(O)
tR / tF
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section.
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TYPICAL PHASE NOISE AT 312.5MHZ AT 3.3V
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k
10Gb Ethernet Filter 312.5MHz
RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.46ps
NOISE POWER dBc Hz
Raw Phase Noise Data
a
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
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PARAMETER MEASUREMENT INFORMATION
2V 2V
2V 2V
VCC VCCA
Qx
SCOPE
VCC VCCA
Qx
SCOPE
LVPECL
nQx
LVPECL
VEE
nQx
-1.3V 0.165V
-0.5V 0.125V
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
nQ Q
Noise Power
t PW
t
PERIOD
Phase Noise Mask
odc =
t PW t PERIOD
x 100%
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
RMS PHASE JITTER
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
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APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843031-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V or 2.5V VCC .01F VCCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843031-01 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p
FIGURE 2. CRYSTAL INPUt INTERFACE
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LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output
VDD
impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER
TO
XTAL INPUT INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
Zo = 50 84 84
1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
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TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C.
2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843031-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS843031-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 105mA = 363.8mW Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 363.8mW + 30mW = 393.8mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.394W * 90.5C/W = 105.6C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA
FOR
8-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
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3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (VCC_MAX - VOH_MAX) = 0.9V
*
For logic low, VOUT = VOL_MAX = VCC_MAX - 1.7V (VCC_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (V
L
CC_MAX
- VOH_MAX))/R ] * (VCC_MAX - VOH_MAX) =
L
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOL_MAX) = [(2V - (V
L
CC_MAX
- VOL_MAX))/R ] * (VCC_MAX - VOL_MAX) =
L
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
TRANSISTOR COUNT
The transistor count for ICS843031-01 is: 2377
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PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.7 5 8 0.1 0 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.5 0 Millimeters Minimum 8 1.2 0 0.1 5 1.05 0.30 0.20 3.1 0 Maximum
Reference Document: JEDEC Publication 95, MO-153
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TABLE 10. ORDERING INFORMATION
Part/Order Number ICS843031AG-01 ICS843031AG-01T ICS843031AG-01LF ICS843031AG-01LFT Marking 31A01 31A01 1A01L 1A01L Package 8 Lead TSSOP 8 Lead TSSOP 8 Lead "Lead-Free" TSSOP 8 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuraiton and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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REVISION HISTORY SHEET Rev A A Table T3 T1 0 Page 2 14 Added OE Function Table. Order Information Table - Added Lead Free marking Description of Change Date 1/23/07 8/1/07
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Europe
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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